register file example

[hashhsah]

I am trying out the test/test_system/test_regfile.py test case, and have some doubts about the converted verilog/vhdl.

There is a process that read from *_assign_namedbits0_wbits[ii] signals:

always @(memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[0], memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[1], memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[2], memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[3], memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[4], memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[5], memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[6], memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[7]) begin: PERIPHERAL_TOP_MEMMAP_PERIPHERAL1_WISHBONE6_ADD0_WISHBONE7_PERIPHERAL_REGFILE0_REGISTERFILE2_GET_ASSIGNS0_REGISTER4_ASSIGN_NAMEDBITS0_BEH_ASSIGN
    integer ii;
    for (ii=0; ii<8; ii=ii+1) begin
        memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_rl[4][ii] = memmap_peripheral1_Wishbone6_add0_Wishbone7_peripheral_regfile0_RegisterFile2_get_assigns0_Register4_assign_namedbits0_wbits[ii];
    end
end

Since *_assign_namedbits0_wbits[ii] contains some ShadowSignals of the named bits, I'm expecting some continuous assignment statements that writes to *_assign_namedbits0_wbits[ii]. However, the assignments are missing.

I wonder if this is expected behavior, a bug in rhea, or a regression in myhdl?
btw, using github master of both myhdl and rhea.