Search results

register file example

Status: Open.

#61 In cfelton/rhea;

· hashhsah opened on Feb 8, 2019

spi_slave_fifo_async

Status: Open.

#59 In cfelton/rhea;

· mngr0 opened on Sep 30, 2018

sdram controller

Status: Open.

#58 In cfelton/rhea;

· hstarmans opened on Jan 11, 2017

[enhancement] Provide board definition and blinky example for Red Pitaya

Status: Open.

#57 In cfelton/rhea;

· sanojb opened on Dec 21, 2016

instructions: xula_blinky_host.py on raspberry pi 3B [solved]

Status: Open.

#56 In cfelton/rhea;

· hstarmans opened on Nov 17, 2016

Support Diligent Adept's 'djtgcfg' utility for flow.program() on applicable Diligent boards

Status: Open.

#55 In cfelton/rhea;

· NickShaffner opened on Aug 20, 2016

Symbol 'MMCME2_BASE' is not supported in target 'spartan6'.

enhancement

Status: Open.

#53 In cfelton/rhea;

· NickShaffner opened on Aug 14, 2016

·  

0.1

ClockManagement's 'enable' parameter is not implemented on Xilinx parts

enhancement

Status: Open.

#51 In cfelton/rhea;

· NickShaffner opened on Aug 14, 2016

·  

0.1

Would be nice if flow.run() provided board information to the top module for things like ClockManagement

question

Status: Open.

#47 In cfelton/rhea;

· NickShaffner opened on Aug 11, 2016

[enhancement] create a skipif synthesis tool not available

enhancement

Status: Open.

#45 In cfelton/rhea;

· cfelton opened on Aug 11, 2016

vga: use the timing parameter class vs. function

enhancement

Status: Open.

#35 In cfelton/rhea;

· cfelton opened on Jul 30, 2016

·  

0.1

travis-ci build matrix

bug

help wanted

Status: Open.

#29 In cfelton/rhea;

· cfelton opened on Jun 19, 2016

·  

0.1