Engineering Projects

Sole engineer responsible for all aspects of the design, production, and testing of two Spartan-6 FPGA designs, used for anode local track processing in the muon endcap.

One design utilizes the CERN VTRX module and CERN GBTX ASIC. The GBTX is used for both data transmission on a 5.12 Gbps optical link, as well as for a novel system for providing a radiation-hard alternative to an EEPROM (which have shown significant issues due to charge pump degradation in the radiation environment of ME1/1). The second design uses the CERN VTTX module to provide twin 3.2 Gbps optical links, along with a larger FPGA than the LX100 card, specifically designed for the high channel-count inner stations of the CMS Muon Endcap.

• github.com/andrewpeck/OALCT-LX150T
• github.com/andrewpeck/OALCT-LX100

I was solely responsible for the fabrication, packaging, and testing of 3200 ASICs which were originally designed by UCLA in 2002. I recovered the design files for the ASIC and contacted vendors to oversee the complete wafer production, dicing, thinning, packaging, as well as re-engineering from scratch all testing hardware, firmware, software, and analysis code.

I also performed characterization of the chip under radiation, using the TAMU reactor as well as the UC Davis Cyclotron.

The test board for production testing of the ASICs uses a Spartan-6 FPGA along with a microcontroller and a custom-designed analog pulse shaping network to provide programmable analog inputs and check the digital response of each one of the 3200 ASICs. Along with the PCB design, I also handled all microcontroller software (C++), analysis software (C++/ROOT), and firmware (Verilog).

I wrote the logic for our ASIC production testing board, implemented in a Spartan-6 FPGA. Used for the successful production testing of 3200 ASICs.

Contributed to the CSC OTMB firmware to incorporate additional trigger data coming from the newly installed GEM chambers into the formation of CSC trigger primitives.

I also designed and implemented a new FPGA algorithm for the CSC trigger primitive generation, which is currently being commissioned and seems to achieve a factor of 2 improvement in bend-angle resolution along with a factor of 4 improvement in position measurement by applying a lookup-table based fit to the hits with zero added latency. I also supervised two students who developed a C++ version of the algorithm which was used for validation of the firmware through a Verilog test bench as well as for performance studies.

• github.com/csc-fw/otmb_fw_code

I managed the fabrication, assembly, testing, and repair of 56 RPC-ALCT-Transition (RAT) boards for the CSC ME4/2 upgrade, which was a preexisting design of which additional circuit boards were needed.

I repaired many dozens of boards for CMS (CFEB, ALCT, TMB, RAT, ALCT Mezzanine, TMB Mezzanine) for maintenance and operation of CSC electronics.

Contributed bug fixes and new features to the CMS EMU online software (C++), mostly relating to the operation of the CSC trigger motherboard and ALCT boards.

• github.com/andrewpeck/emu

Developed a Monte Carlo based model of the CSC TMB readout electronics to understand and predict the effects of increasing luminosity and pileup on the DAQ requirements of the TMB. The model was compared to analytic methods based on standard queue modeling and coincided well.

• github.com/andrewpeck/tmb_queue_model

Worked on the construction and testing of 72 Cathode Strip Chambers for installation in the CMS ME4/2 system. I was responsible for the final quality control of the electronics, doing the final testing and sign off on the assembled chambers.

I was also involved in the factory QA for the production of the bare copper panels for CSC production.

I designed, simulated, implemented, and tested firmware targeting Artix-7 and Virtex-6 FPGAs which takes in ~112 Gbps of data on differential links and uses a custom design zero suppression scheme to perform lossy 14:1 data concentration in an algorithmic latency budget of only 100 ns. The output data is concentrated onto an optical fiber at 4.0 Gbps. The firmware suite was largely triplicated using TMR to make it more robust to radiation.

Additionally, I worked on the firmware for the backend readout of the GEM detectors. As part of this effort, we created a central repository that merged the source code of the front-end and back-end FPGAs, allowing us to reduce code duplication and maintain synchronization between firmware versions:

• gitlab.cern.ch/emu/0xbefe

I designed and tested the the ME0 “segment finder”, which is a custom firmware block that does multi-layer pattern recognition and sorting to identify patterns of hits corresponding to charged particles passing through the detector. This design targeting a Xilinx VU13P FPGA and is now in the early stages of verification in chip.

In the late stages of the algorithm design I began working with a physicist in performance studies of the algorithm. Despite its “naive” design implemented by a solo engineer it achieved over 99% efficiency and met physics requirements.

• github.com/andrewpeck/me0sf

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I designed two generations of an lpGBT-based on-chamber DAQ + trigger concentrator for ME0. I also worked on the firmware and low-level software for integrating the board into the ME0 detector:

• github.com/andrewpeck/OH0
• twiki.cern.ch/twiki/bin/viewauth/CMS/ME0ASIAGO

I co-designed the CMS Endcap Timing Layer readout board, featuring a variety of CERN ASICS (LPGBT, SCA, LinPOL12, and VTRX+). The board is required to fit in a tight space, so extensive work was done to optimize the use of the space to ensure that the system would be feasible. This optimization ended up completely re-thinking the electronics layout and significantly changing the overall design.

I wrote the firmware and the software for a KCU105-based control and readout system for the readout board, which will be used for both readout board and module testing.

• gitlab.cern.ch/cms-etl-electronics/module_test_fw

I co-designed the front-end readout hybrid, which will host a wirebonded 256 pixel Low Gain Avalanche Diode array with a readout TDC achieving 40 ps time resolution.

I am co-developing the control software (Python) for the ETL readout / module testing system. I wrote an initial version of the software that was used for board testing and firmware development; the software has largely been taken over by a postdoc but I am still involved in most of its developments.

• https://gitlab.cern.ch/cms-etl-electronics/module_test_sw

I worked extensively in the Endcap Timing Layer on the overall system design, integration of services, mechanics, board-to-board interfaces, etc to bring the design from a conceptual goal to a realistic implementation.

I participated in the design of the GAPS master trigger system, a Kintex-7 based FPGA system responsible for receiving 400 channels of detector data and making low-latency trigger decisions to identify decay signatures. I worked with the project manager and another engineer to define the system specifications and did detailed schematic and layout reviews. I worked on board testing and debug, and wrote all firmware for the FPGA (VHDL). The firmware is responsible for deserializing data from 100 asynchronous serial lines, performing low-latency trigger logic to identify characteristic decay signatures, and serializing trigger information to the readout boards. The firmware also has a GbE UDP interface for control and readout of the trigger information, SPI interfaces for monitoring. I also created control software for the master trigger in Python.

• gitlab.com/ucla-gaps-tof/firmware

I was involved in the experiment since it was in the prototype stage, and played a major role in guiding the design of the readout and trigger system for the TOF. I trained and supervised a series of junior engineers as well as a postdoc in the conceptual design, schematic capture, and layout of the “Readout Board”, a PCB hosting a 5 Gsps 8 channel waveform digitizer ASIC along with a Zynq SOC that is used for control and data acquisition. I participated heavily in all steps of the design, debug, and software development by advising the junior engineers who were doing much of the day-to-day work. Additionally, I was solely responsible for writing all the readout firmware (Verilog/VHDL) running on the FPGA that is responsible for reading and controlling the waveform digitizer, receiving serialized triggers, packetizing and buffering data and transferring it into the processing system through DMA.

• gitlab.com/ucla-gaps-tof/drs4-board
• gitlab.com/ucla-gaps-tof/firmware

I wrote a command-line implementation of the DAQ software for the DRS ASIC evaluation board. I also wrote analysis code (using ROOT) and performed extensive characterization to understand the timing resolution achievable with our PMTs when reading out with the DRS ASIC.

• github.com/andrewpeck/drs4-daq

• Designed a board for precision amplification and digitization of analog signals coming from a commercial position-sensitive device module, which is currently used in the alignment system of the CTA-SCT prototype telescope in Arizona.
  • The board had tight mechanical requirements to fit in the available envelope and had to be realized as 4 printed circuit boards interconnected into a three-dimensional array

• PSD Readout Software (microcontroller): Wrote microcontroller software for digitizing and reading out measurements from a position sensitive detector (PSD) which was used in the alignment system of the telescope.
  • github.com/andrewpeck/psd_readout

• Designed boards for distribution and monitoring of high current, low-voltage for the panel-to-panel alignment system of the CTA-SCT
• Designed a board for interfacing with a microcontroller to connect ADCs to the PEDB power supply board current sensors

• Wrote a suite of software in C++ for low-level hardware control of the CTA SCT mirror control board. For speed, the software was required to interface directly with the registers of the embedded CPU, bypassing all Linux drivers.
  • github.com/andrewpeck/CTA-Mirror-Control

• Worked with undergraduate students to write the microcontroller software for controlling the power and ethernet distribution box.
  • github.com/andrewpeck/pedbFirmware

Reverse-engineered a closed-source Windows driver and ported all functionality for controlling hardware modules to Linux.

• github.com/andrewpeck/piusb

Dimetix Laser Sensor: Created a software tool for controlling and reading back a precision laser rangefinder. The vendor provided a Windows tool but a Linux utility was needed for use on the CTA SCT telescope.

• github.com/andrewpeck/dimetix-lasersensor

(2017–2019)

I assisted a (then) junior engineer to build several smaller prototypes along with a complex electronics design (OCEAN, shown below) which features a large Xilinx ZU19EG FPGA, high current power supplies, SATA, USB, DDR4, Gigabit Ethernet, display port, and 72 optical links operating at 25 Gbps, while confirming to the ATCA specification.

(2014–2016)

Developed many small projects for the Niemann plasma lab at UCLA. Some examples that I can recall are:

• TTL Line Driver: designed a small interface board for connecting an FPGA to a legacy plasma control system requiring 15V logic

  

• Modulator Driver: developed a module (analog summer) that provides a programmable DC offset to an analog input signal, needed for biasing a driving circuit of a laser

  

• POF receiver: designed a small board that digitizes signals photodiode (receiving trigger data over POF) and produces a low jitter output capable of driving 5V 50 ohm loads

  

• POF driver: designed a small board that takes TTL inputs on BNC and drives a plastic optical fiber
• Repair: repaired and maintained many legacy instruments which were commercially produced but no longer supported

(2015)

Developed a custom PCB and housing for an optical sensor (extracted from high-performance gaming mice) as part of a custom-made motion-sensing application for Neurophysics research

(2023)

Developed a prototype solenoid driver with a PWM-based spike and hold driving circuit.

(2014–2016)

Designed and built a PCB and enclosure for a small digitally controlled high-voltage pulser used as a low-cost replacement for expensive bio-medical electroporation devices

Also wrote a simple microcontroller code that provides “electroporator” functionality, which involves using a foot-pedal to deliver high voltage pulses of programmable voltage, duration, and quantity for use in biomedical research.

• github.com/andrewpeck/electroporator

(2020–2023)

For a small fraction of my time, I worked on the “Apollo project”, a common ATCA platform used in the CMS Track Trigger, CMS Tracker readout, and the ATLAS L0MDT.

I did in-depth schematic and layout reviews for the Apollo ATCA Service and Command Modules, and also ported the OpenIPMC firmware for the Apollo ATCA platform. The IPMC firmware is responsible for all critical low-level control and monitoring of the Apollo ATCA blades.

• gitlab.com/BU-EDF/openipmc-fw

(2014–2016)

• Developed a pair of small boards to perform digitization of analog signals for remote monitoring of an electron accelerator
• Developed a small board using a monostable multivibrator and some discrete logic components to create a pot-programmable “hold-off” to prevent retriggering of a device for use in a particle beam experiment
• Developed an amplifier for driving analog signals over long (~100m) coaxial cables.
• Reverse-engineered and re-created several hand-built legacy circuit boards and replaced them with printed circuit boards
• Repaired several legacy instruments that were commercially produced but no longer supported by the vendor

I designed an RF PID controller based on a design taken from a paper as part of a condensed matter experiment

• Created a high-voltage, low-current piezo driver that uses a low-voltage DC reference to produce an analog control signal for piezo steppers
• Created a board for interfacing with an Arduino to allow for high-current control of valve actuators, as part of an effort to increase lab automation
• Created a power distribution and monitoring board

Built a small BJT-based amplifier used by students in a lower-division teaching lab. I also repaired numerous instruments used in the UCLA teaching lab

• Designed a microcontroller based board that controlled precision ADCs and DACs and implemented a software control that was part of a PID feedback loop for a custom-designed high voltage power supply. The microcontroller also connected to a LCD touchscreen which was used to control the power supply

• Wrote a microcontroller-based program which runs a GUI touchscreen that controls a custom built high voltage power supply.

  

• Did the box assembly for several multichannel HV systems.

  

(2012)

While an undergraduate I designed, built, and programmed a system that used an FPGA evaluation board to drive motor-drivers that toggle a network of RF switches as part of the ANITA ground pulsing calibration system

Worked on a system for mapping XML register tables into a hierarchical VHDL record which is automatically mapped into an AXI slave

• github.com/BU-Tools/uHAL_AXI_regmap

Worked on a system for mapping XML register tables into automatically generated Wishbone decoders that are mapped onto VHDL registers.

• github.com/andrewpeck/regtools

I made significant contributions to the HOG (HDL on Git) firmware build system. It is a cross-platform, open source firmware build system currently used throughout the LHC and in other experiments.

• hog-user-docs.web.cern.ch
• gitlab.com/hog-cern/hog

I also created an Emacs package for working with Hog managed projects, which provides various facilities including generation of LSP configurations, highlighting of Hog src files, commands to open/compile Hog projects.

• github.com/andrewpeck/hog-emacs

I worked on the development of the prototype TDC/readout system for the EMPHATIC ARICH detector. Developed the readout firmware and overall firmware infrastructure

• gitlab.com/emphatic-arich/firmware