Implement optimized movemasks for NEON #1236
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While the scalar post-processing required to obtain one bit per lane makes this more expensive than directly supporting variable-sized bit groups (as done in Zstandard[^1]), the result is still an improvement over the current lane-by-lane algorithm. [^1]: See facebook/zstd#3139, namely `ZSTD_row_matchMaskGroupWidth`.
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I've suggested an improvement of the 64 bit version there: https://godbolt.org/z/b7henc933 |
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Applied, thank you for the suggestion. I will fix the GCC build in a moment. |
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FYI, I'm working on the aarch64 version in #1237 |
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serge-sans-paille
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Dec 28, 2025
As a complement to #1236
serge-sans-paille
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Dec 28, 2025
As a complement to #1236
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LGTM once CI is good. I'll squash everything in a single commit and merge. Thanks for this! |
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Great, thank you for your assistance. |
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While the additional instructions required to obtain one bit per lane
make this more expensive than directly supporting variable-sized bit
groups (as done in Zstandard1), the result is still an improvement
over the current lane-by-lane algorithm.
To reduce duplication,
XSIMD_LITTLE_ENDIANis moved frommath/xsimd_rem_pio2.hpptoconfig/xsimd_config.hpp, and will now beavailable outside the defining header.
Footnotes
See [lazy] Optimize ZSTD_row_getMatchMask for levels 8-10 for ARM facebook/zstd#3139, namely
ZSTD_row_matchMaskGroupWidth. ↩