GitHub - tenacex/mips: A 5-stage pipelined MIPS processor

Name		Name	Last commit message	Last commit date
Latest commit History 28 Commits
tests		tests
alu-harness.circ		alu-harness.circ
alu.circ		alu.circ
assembler.py		assembler.py
cpu.circ		cpu.circ
logisim.jar		logisim.jar
mem.circ		mem.circ
regfile-harness.circ		regfile-harness.circ
regfile.circ		regfile.circ
run-sanity-test.sh		run-sanity-test.sh
run.circ		run.circ
test.hex		test.hex
test.s		test.s