https://github.com/benmahr/RenZhengfei

Digital timing diagram editor

Low Density Parity Check Decoder

HDL libraries and projects

Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)

Parallel Array of Simple Cores. Multicore processor.

Verilog library for ASIC and FPGA designers

Verilog UART

Verilog Ethernet components for FPGA implementation

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…

本项目曾冲到全球第一，干货集锦见本页面最底部，另完整精致的纸质版《编程之法：面试和算法心得》已在京东/当当上销售

Google 开源项目风格指南 (中文版)

Event notification library

LevelDB is a fast key-value storage library written at Google that provides an ordered mapping from string keys to string values.

A JIT assembler for x86/x64 architectures supporting FPU, MMX, SSE (1-4), AVX (1-2, 512), APX, and AVX10.2

matplotlib: plotting with Python

The official Linux kernel from Xilinx

Python Productivity for ZYNQ

Symulacja modulacji MSK oraz GMSK

Google Chrome, Firefox, and Thunderbird extension that lets you write email in Markdown and render it before sending.

中文 Python 笔记

A search tool helps dev to solve the naming things problem.