- Tempe, Arizona, US
- https://www.linkedin.com/in/nitin-mishra-76a48353/
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GSOC_TensorCore
GSOC_TensorCore PublicTensorCore Vector Processor for Deep Learning - Google Summer of Code Project
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tnoc
tnoc PublicForked from taichi-ishitani/tnoc
Network on Chip Implementation written in SytemVerilog
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UVM-APB_RAL
UVM-APB_RAL PublicForked from JoseIuri/UVM-APB_RAL
This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
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AMBA_APB_SRAM
AMBA_APB_SRAM PublicForked from courageheart/AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
SystemVerilog
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