ABC: System for Sequential Logic Synthesis and Formal Verification

Learn how to design large-scale systems. Prep for the system design interview. Includes Anki flashcards.

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A High-performance Timing Analysis Tool for VLSI Systems

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

An Open Source Machine Learning Framework for Everyone

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Открытое письмо специалистов IT-индустрии в защиту фигурантов «московского дела»

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A modern editor with a backend written in Rust.

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