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1. VexRiscv VexRiscv Public

   Forked from SpinalHDL/VexRiscv

   A FPGA friendly 32 bit RISC-V CPU implementation

   Assembly

2. serv serv Public

   Forked from olofk/serv

   SERV - The SErial RISC-V CPU

   Verilog

3. Accelerating-CNN-with-FPGA Accelerating-CNN-with-FPGA Public

   Forked from WalkerLau/Accelerating-CNN-with-FPGA

   This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

   C++

4. riscv riscv Public

   Forked from ultraembedded/riscv

   RISC-V CPU Core (RV32IM)

   Verilog

5. 80x86 80x86 Public

   Forked from jamieiles/80x86

   80186 compatible SystemVerilog CPU core and FPGA reference design

   C++

6. oldland-cpu oldland-cpu Public

   Forked from jamieiles/oldland-cpu

   Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

   Verilog