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Pull request overview
This PR fixes signal width specification bugs in AXI5 mixin implementations to ensure compliance with the AXI specification. The changes correct missing width parameters for several signals that were either defaulting to width 1 or had duplicate/incorrect port declarations.
Changes:
- Removed duplicate
TAGport declaration inAxi5MemRespDataTagSignals - Added missing width parameters to
MMUSID,MMUSSID, andSUBSYSIDsignals
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Description & Motivation
Miscellaneous bugs in the AXI5 mixins. Mostly just bad signal widths but took the opportunity to check everything for consistency.
Related Issue(s)
N/A
Testing
No explicit testing since all of the changes are primarily just fixing of widths which is trivial.
Backwards-compatibility
These are all unequivocal bugs that render the signals non-compliant with the AXI spec so not backwards compatible by construction. However, very likely this won't negatively impact any users.
Documentation
No explicit documentation needed - comes from AXI spec.