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1. FYP--Risc-V-32-bit-Matrix-Mac FYP--Risc-V-32-bit-Matrix-Mac Public

   Forked from theuppercaseguy/FYP--Risc-V-32-bit-Matrix-Mac

   A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations

   Verilog 1

2. Advanced-Physical-Design-using-OpenLANE-and-Skywater-130-PDK Advanced-Physical-Design-using-OpenLANE-and-Skywater-130-PDK Public

   Forked from prajwalita17/Advanced-Physical-Design-using-OpenLANE-and-Skywater-130-PDK

   This repository contains a step by step procedure to the complete RTL2GDSII flow of PICORV32A RISC-V core design using open-source EDA tool OpenLANE and Google-Skywater’s first manufacturable open …

3. axi-crossbar axi-crossbar Public

   Forked from dpretet/axi-crossbar

   An AXI4 crossbar implementation in SystemVerilog

   SystemVerilog

4. Canary-RV32IMA Canary-RV32IMA Public

   Forked from SiddantY/Canary

   Hardware Scheduled Dual Core RISC-V (OOO IMAC + Pipelined IA) Processor with a snoop bus interconnect (MESI Protocol) -- all in SystemVerilog

   Assembly

5. picorv32 picorv32 Public

   Forked from YosysHQ/picorv32

   PicoRV32 - A Size-Optimized RISC-V CPU

   Verilog

6. scr1 scr1 Public

   Forked from syntacore/scr1

   SCR1 is a high-quality open-source RISC-V MCU core in Verilog

   SystemVerilog