fix: UDP streamer + demo

[chmousset]

The UDP streamer TX path didn't correctly set the packet size, and the bench's example didn't use the right clock domain.
The bench now works both on the TX and RX paths.

> python bench/arty.py --build --load
[...]
fpga_program
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Info : clock speed 25000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
> ./bench/test_udp_streamer.py --switches --leds
# it blinks!
Switches value: 0x01
Switches value: 0x01
Switches value: 0x01
Switches value: 0x01
Switches value: 0x05
Switches value: 0x05
Switches value: 0x05
Switches value: 0x05
[...]