Stars
Communication framework for RTL simulation and emulation.
Automatic generation of real number models from analog circuits
A framework for FPGA emulation of mixed-signal systems
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
YMODEM written by Python - 用Python实现的YMODEM通讯协议
Command line tools for working with files for Oric-1 and Oric-Atmos
SystemC/TLM-2.0 Co-simulation framework
QEMU libsystemctlm-soc co-simulation demos.
Modular hardware build system
Did My Code Execute - C/C++ source code level tracer
Random instruction generator for RISC-V processor verification
Verilator open-source SystemVerilog simulator and lint system
Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G





