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Communication framework for RTL simulation and emulation.

Python 306 24 Updated Dec 17, 2025

Universal Memory Interface (UMI)

Verilog 156 15 Updated Dec 22, 2025

Automatic generation of real number models from analog circuits

Python 47 13 Updated Apr 2, 2024

A framework for FPGA emulation of mixed-signal systems

Python 38 10 Updated Jul 28, 2021

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

SystemVerilog 50 9 Updated Jan 13, 2021

Provides automation scripts for building BFMs

Python 16 1 Updated Apr 19, 2025

YMODEM written by Python - 用Python实现的YMODEM通讯协议

Python 99 55 Updated Jul 19, 2024

Command line tools for working with files for Oric-1 and Oric-Atmos

C++ 4 1 Updated Apr 13, 2025

SystemC/TLM-2.0 Co-simulation framework

Verilog 263 81 Updated May 21, 2025
SystemVerilog 1 Updated Nov 6, 2022

QEMU libsystemctlm-soc co-simulation demos.

C++ 159 60 Updated May 21, 2025

PCI Express controller model

C 71 19 Updated Oct 5, 2022

TBM Bare metal tests

C 18 6 Updated Jun 3, 2025

Modular hardware build system

Python 1,116 115 Updated Jan 1, 2026

Qemu Etrace

C 15 4 Updated May 21, 2024

Did My Code Execute - C/C++ source code level tracer

Python 21 8 Updated Apr 9, 2025

Random instruction generator for RISC-V processor verification

Python 1,232 367 Updated Oct 1, 2025

Verilator open-source SystemVerilog simulator and lint system

SystemVerilog 3,269 729 Updated Dec 31, 2025
C++ 15 4 Updated May 29, 2020

Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

C 278 177 Updated Nov 20, 2025

LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G

C 40 12 Updated Apr 3, 2023

TLMu - Transaction Level eMulator

C 36 26 Updated Nov 27, 2014