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[mono][jit] Adding Vector128.Dot as intrinsic for arm64. #84245

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Merged
jandupej merged 8 commits into from
Apr 17, 2023
Merged

[mono][jit] Adding Vector128.Dot as intrinsic for arm64. #84245

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d1d27c6
[mono][jit] Adding Vector128.Dot as intrinsic for arm64.
jandupej Apr 3, 2023
acdd6a9
Fixed the (u)int64 case, which now falls back to unoptimized code.
jandupej Apr 13, 2023
b8c58a4
Merge branch 'main' into arm64-simd-dor
jandupej Apr 13, 2023
5275a16
Fixed klass.
jandupej Apr 13, 2023
a15d443
Disabled the intrinsic for native ints, enabled for LLVM.
jandupej Apr 14, 2023
3a6a284
Fixed COMPILE_LLVM condition.
jandupej Apr 14, 2023
a67e468
Relaxing non-LLVM restriction for WASM.
jandupej Apr 17, 2023
96abce2
Merge branch 'main' into arm64-simd-dor
jandupej Apr 17, 2023
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2 changes: 1 addition & 1 deletion src/mono/mono/mini/simd-arm64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ SIMD_OP (128, OP_XBINOP, OP_FMAX, WTDSS, _UNDEF,
SIMD_OP (128, OP_XBINOP, OP_IMIN, WTDSS, arm_neon_smin, arm_neon_smin, arm_neon_smin, _SKIP, _UNDEF, _UNDEF)
SIMD_OP (128, OP_XBINOP, OP_IMIN_UN, WTDSS, arm_neon_umin, arm_neon_umin, arm_neon_umin, _SKIP, _UNDEF, _UNDEF)
SIMD_OP (128, OP_XBINOP, OP_FMIN, WTDSS, _UNDEF, _UNDEF, _UNDEF, _UNDEF, arm_neon_fmin, arm_neon_fmin)
SIMD_OP (128, OP_XBINOP, OP_IMUL, WTDSS, arm_neon_mul, arm_neon_mul, arm_neon_mul, arm_neon_mul, _UNDEF, _UNDEF)
SIMD_OP (128, OP_XBINOP, OP_IMUL, WTDSS, arm_neon_mul, arm_neon_mul, arm_neon_mul, _UNDEF, _UNDEF, _UNDEF)
SIMD_OP (128, OP_XBINOP, OP_FMUL, WTDSS, _UNDEF, _UNDEF, _UNDEF, _UNDEF, arm_neon_fmul, arm_neon_fmul)
SIMD_OP (128, OP_XBINOP, OP_FDIV, WTDSS, _UNDEF, _UNDEF, _UNDEF, _UNDEF, arm_neon_fdiv, arm_neon_fdiv)
SIMD_OP (128, OP_XBINOP_FORCEINT, XBINOP_FORCEINT_AND, WDSS, arm_neon_and, arm_neon_and, arm_neon_and, arm_neon_and, arm_neon_and, arm_neon_and)
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12 changes: 9 additions & 3 deletions src/mono/mono/mini/simd-intrinsics.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1324,7 +1324,6 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
case SN_ConvertToUInt32:
case SN_ConvertToUInt64:
case SN_Create:
case SN_Dot:
case SN_GetElement:
case SN_GetLower:
case SN_GetUpper:
Expand All @@ -1342,7 +1341,7 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
}
#endif

MonoClass *klass = cmethod->klass;
MonoClass* klass = fsig->param_count > 0 ? args[0]->klass : cmethod->klass;
MonoTypeEnum arg0_type = fsig->param_count > 0 ? get_underlying_type (fsig->params [0]) : MONO_TYPE_VOID;

if (cfg->verbose_level > 1) {
Expand Down Expand Up @@ -1557,10 +1556,17 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
case SN_Dot: {
if (!is_element_type_primitive (fsig->params [0]))
return NULL;
#if defined(TARGET_WASM)
if (!COMPILE_LLVM (cfg) && (arg0_type == MONO_TYPE_I8 || arg0_type == MONO_TYPE_U8))
return NULL;
#elif defined(TARGET_ARM64)
if (!COMPILE_LLVM (cfg) && (arg0_type == MONO_TYPE_I8 || arg0_type == MONO_TYPE_U8 || arg0_type == MONO_TYPE_I || arg0_type == MONO_TYPE_U))
return NULL;
#endif

#if defined(TARGET_ARM64) || defined(TARGET_WASM)
int instc0 = type_enum_is_float (arg0_type) ? OP_FMUL : OP_IMUL;
MonoInst *pairwise_multiply = emit_simd_ins_for_sig (cfg, klass, OP_XBINOP, instc0, arg0_type, fsig, args);

return emit_sum_vector (cfg, fsig->params [0], arg0_type, pairwise_multiply);
#elif defined(TARGET_AMD64)
int instc =-1;
Expand Down