JIT: Assertion failed '(op2->GetRegNum() != targetReg) || (op1Reg == targetReg)' during 'Generate code'

[jakobbotsch]

// Generated by Fuzzlyn v2.2 on 2024-08-01 15:50:23
// Run on X64 Linux
// Seed: 16776152078868034128-vectort,vector128,vector256,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86avx512fx64,x86bmi1,x86bmi1x64,x86bmi2,x86bmi2x64,x86fma,x86lzcnt,x86lzcntx64,x86pclmulqdq,x86popcnt,x86popcntx64,x86sse,x86ssex64,x86sse2,x86sse2x64,x86sse3,x86sse41,x86sse41x64,x86sse42,x86sse42x64,x86ssse3,x86x86base
// Reduced from 17.3 KiB to 0.4 KiB in 00:00:34
// Hits JIT assert in Debug:
// Assertion failed '(op2->GetRegNum() != targetReg) || (op1Reg == targetReg)' in 'Program:M1(short)' during 'Generate code' (IL size 18; hash 0xb20f93e4; MinOpts)
// 
//     File: /__w/1/s/src/coreclr/jit/hwintrinsiccodegenxarch.cpp Line: 2242
// 
using System;
using System.Runtime.CompilerServices;
using System.Numerics;
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.X86;

public class Program
{
    public static void Main()
    {
        M1(0);
    }

    public static void M1(short arg0)
    {
        Sse42.Crc32(Bmi2.ParallelBitDeposit(0, 0) % 0, (uint)arg0);
    }
}

cc @dotnet/jit-contrib

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[amanasifkhalid]

From offline discussion with @EgorBo, I agree this assert seems overzealous. I don't see any requirement that the source and destination registers cannot be the same in the docs for the CRC32 instruction, and it doesn't seem important that op1Reg != targetReg in such cases -- we'll just move op1Reg into targetReg beforehand. I think it's safe to remove this. (Edit: see #105833).