• sbt version in this project: 1.10.11 (see project/build.properties)
• see chisel/scala version in build.sbt
• For FIR/IIR, scipy is used.

• gtkwave / surfer (waveform visualization)
• verilator (generating executable files for testbench)
• fzf (optional)

• icarus & cocotb (only tested under cocotb 1.9.2)
• fzf (optional)

• Use Vivado (precise)
• Pls use the updated yosys or there might be problems.(rough)

To generate systemVerilog, write demos under app/... , and run

make run

or

sbt app/run

Run test using verilator and gtkwave / surfer through tb.sh

make tb # (FZF=true)

Make sure that the tb file located in sims/tb

or using

make cocotb # (FZF=true)

for cocotb through cocotb.sh

Similarly, make sure that the py scripts are located in sims/cocotb and make sure you have cocotb env, activating a venv with uv is recommended.

Run sta using Yosys or Vivado through sta-yosys.sh(sta-vivado.sh) with Xilinx toolchain.

make sta # (FZF=true STA_TOOL=yosys(vivado))

make localpublish

or just use sbt to install is also ok.

• chisel-template
• FFT
• AXI-IF
• hardfloat

Copyright 2025-2026 dashygo097

Licensed under the Apache License, Version 2.0. See LICENSE for details.