Verilog AXI components for FPGA implementation

A maintained ctags implementation

TLS/SSL and crypto library

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

A Python wrapper for librtlsdr (a driver for Realtek RTL2832U based SDR's)

jpeg encoder

Video Stream Scaler

Getting Started with Xilinx ML Suite

Python on Zynq FPGA for Convolutional Neural Networks