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Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Python 3,436 449 Updated Oct 28, 2024

SERV - The SErial RISC-V CPU

Verilog 1,757 247 Updated Feb 19, 2026

VHDL implementation of Pipelined Wishbone B4 interconnect

VHDL 2 Updated Dec 5, 2024

A study of soft-core CPUs for use with FPGA designs

Verilog 2 Updated Dec 6, 2024

Small portable AES128/192/256 in C

C 4,866 1,382 Updated Oct 4, 2024