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Varunkumar0610 / RISC-V-32I-5-stage-Pipeline-Core

Implementation of 5 Stage 32I RISC V Pipeline Processor.

Verilog 12 4 Updated Sep 6, 2024

Varunkumar0610 / RISC-V-Single-Cycle-Core

This repository consists of Load, Store and Read word data paths using a Single Cycle Core.

Verilog 3 Updated Sep 2, 2024