Design Verification Engineer | SystemVerilog, UVM, Python, Perl | Interested in SoC verification, coverage closure, and automation
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Silicon Motion Technology Corporation
- Taiwan, Taipei
- in/chih-wei-hsu-harvey-08a463134
Pinned Loading
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MapleSyrupUVM
MapleSyrupUVM PublicA personal project for exploring reusable UVM testbench generation and automation.
Python
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sample_dut_with_uvm
sample_dut_with_uvm PublicA personal learning repository for practicing SystemVerilog and UVM concepts through small examples.
HTML
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SystemOnChip_Xilinx_Zynq
SystemOnChip_Xilinx_Zynq PublicZynq/SoC notes and experiments for video and image-processing integration on FPGA platforms.
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VideoProcessing
VideoProcessing PublicGraduate-school VHDL project for video-processing pipeline design and FPGA-based implementation.
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