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Implementatoin of a simple SDRAM controller for target platform of DE1-SoC
Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v
A lightweight, command-line wget clone built with Go. Efficient and fast, this tool mirrors the core functionality of wget, with minimal dependencies and optimized performance for file downloads.
A Tiny Linux Distro ~ 3MB just Tiny Kernel + Unix User Space
Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Packaged open-source IP blocks and tools for easily assembling system-on-chip designs
🦄 Open source interfaces for the Uniswap protocol
edkey allows you to write ED25519 private keys in the OpenSSH private key format
JavaScript Client-Side Bitcoin Wallet Generator
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Installer Microsoft Office For MacOS
Implementing a RISC-V CPU on FPGA(Cyclone II)
A set of minimal dependency bootstrap binaries
Build a minimal multi-tasking OS kernel for RISC-V from scratch
Tiny RISC-V machine code monitor written in RISC-V assembly.
Minimal bare-metal RISC-V assembly code with UART output for execution in QEMU
Make public some compiled clang-format releases
Toolchain for the RISC-V simulator. Currently consists of just a RISC-V assembler.