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Measure clk-q delay, setup time and time for latch with unit inverter at the output.
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Save the flip-flop schematic as an image and report.
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Vary vdd and plot clk-q delay.
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Vary vdd and plot setup time.
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Check timing for long interconnect.
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Check the vdd limits for long interconnect.
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More..
In the git repo, there is a folder called Reports. You can place all outputs (data, plots etc.) in the HW3 sub folder. Once you are done with your content, place the final PPT in the submission subfolder. Name your ppt as part1a or part1b as the case maybe.