The SPEC CPU 2017 results for rate and speed, with instructions and custom interfacing methodology with Valgrind

The official repository for the gem5 computer-system architecture simulator.

Control the mouse pointer with the keyboard on Wayland.

CH32V203 is an industrial-grade enhanced low-power,small-medium capacity general-purpose MCU based on 32-bit RISC-V core

A tool enabling easy and bulk download of UIL Academics contest materials and data files.

A hacker's file manager with VIM inspired keybind

Curated list of Polybar

Scraper for (most) Academic UIL events

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

A simple superscalar out-of-order RISC-V microprocessor

A FPGA friendly 32 bit RISC-V CPU implementation

A controls library for vexide.

Open-source Rust runtime for VEX V5 robots.

x86_64 Assembly multithreading from scratch on x64 Linux environments

RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.

// Source : ISO

Cross-platform Rust rewrite of the GNU coreutils

A new actively maintained version of Protobot

Original Apollo 11 Guidance Computer (AGC) source code for the command and lunar modules.

Vex (Anti) Innovation Creator

A full featured, fast Command Line Argument Parser for Rust

Resources to learn embedded systems engineering.

How to create an OS from scratch

Writing an OS in Rust

Turn your smartphone into presentation remote controller

Blazingly fast retained layout engine for Bevy ECS.

An experimental pure-Rust x86 bootloader