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NASSCOM-Packaging

Repository for the lab exercises of the "VSD NASSCOM Semiconductor Packaging Workshop" (03/28/2025-04/06/2025 Cohort).

Module 1 - Packaging Evolution: From Basics to 3D Integration

There are no exercises prescribed for this module.

Module 2 - From Wafer to Package: Assembly and Manufacturing Essentials

There are no exercises prescribed for this module.

Module 3 - Labs: Thermal Simulation of Semiconductor Packages with ANSYS

The objective of this lab is to model a FlipChip BGA package and perform a thermal simulation in the Ansys Electronics Desktop (AED) environment. The phases involved are the following:

  1. Start the Ansys Electronics Desktop Student software
  2. Set up a FlipChip BGA package
  3. Thermal definitions and material power sources
  4. Meshing and running the thermal analysis
  5. Explore results

1 Start the Ansys Electronics Desktop Student software

When starting the Ansys Electronics Desktop software, the main window will display quick access buttons for its different tools (HFSS, Q3D, Circuit, Icepak, Maxwell, Simplorer). The one that will be used in the rest of this lab is Icepak.

ansystart

By clicking the Icepak button, a new Icepak design is created into the project and we navigate into the Icepak environment:

icepakstart

From the Icepak design the necessary menus for different parts of the flow are accessible, for instance: 3D component definition, model, thermal, monitor, mesh, analysis, results.

2 Set up a FlipChip BGA package

The software has pre-defined models of common package formats to avoid having to create them from scratch. To incorporate a FlipChip BGA into the design, we just need to right click on the Icepak design and follow the route: Toolkit-->Geometry-->Packages-->Flipchip_BGA

ansysflipchiproute

A new window "Create Flipchip BGA Package" is displayed, where the datasheet information of the package to be modelled needs to be entered in four tabs: Dimensions, Substrate, Solder and Die. For this lab exercise we will use the defaults provided by Ansys.

Dimensions

The package will be oriented in the XY plane, centered in the coordinate origin (xS,yS,zS) = (0.0,0.0,0.0), 15 mm long on the X and Y sides, with a package thickness of 1.6 mm. The model type is "Detailed" with full symmetry.

flipchipdimensions

Substrate

We will use 2 layers with 0.36 mm thickness. For the traces, Cu-Pure as material with 0.033 mm thickness, 55% top trace coverage, 0% bottom trace coverage, 0% 1st internal layer coverage, 0% 2nd internal layer coverage. No thermal vias will be used, 0.2 mm diameter and 0.05 mm plate thcikness for the rest.

flipchipsubstrate

Solder

We will use a full array with 14 rows in each coordinate plane, no suppresed and no central rows. The material for the balls will be "Solder-pb50_sn50", with a diameter and height of 0.5 mm each and a ball pitch of 1.0 mm.

flipchipsolder

Die

For thermal simulation purposes the die will be considered as a 2D thermal source with a power of 1 W. The area of the die is 8.56 x 856 mm2 and the material "Si-typical" . The underfill will have a bump size of 0.01 mm and "Flipchip underfill" as material. No heatsink will be used.

flipchipdie

Model creation

After filling the four tabs and clicking OK the model of the FlipChip BGA package is created. Navigating in the model pane we can observe the model (top hierarchy) or inspect every element, for example: ball group, substrate, die, underfill.

flipchipmodel flipchipballgroup flipchipsubstrate2 flipchipdie2 flipchipdieunderfill

The design list can be checked by double-clicking on the "Model" element under the Icepack project

designlist

3 Thermal Definitions and Material Power Sources

The next step is defining the boundary conditions for the thermal analysis. We can inspect them under the "Thermal" element of the Icepak project structure.

thermalviewinspect

The "Thermal" element is not empty: two of the boundary conditions were already specified when adding the FlipChip BGA package model: the die power source and the condition given by the trace thickness. We check that they have the correct parameters (1W power for the die source and 0.033 mm thickness for the trace):

thermaldiebc themaltrace

We still need to add a thermal boundary condition in the substrate. For this, we right-click on the Flipchip_BGA1_substrate element and follow the route "Assign thermal--> source"

thermalsubstrateroute1

In the next window we configure "Fixed Temperature" as the type of Thermal Condition and we fix it to AmbientTemp

thermalsubstrateroute2

A new boundary condition is added in the "Thermal" group as "Source1":

newsource1

Since there is an overlap warning with the boundary condition "Flipchip_BGA1_trace1" we remove this one and remain with only two of them: "Flipchip_BGA1_die_source" and "Source1"

thermalremoved

The next step is adding the necessary monitors. We will add three point temperature monitors: one in the die, one in the substrate and one in the underfill. The process to add a monitor is right clicking on the corresponding element and then following the route "Assign Monitor --> Point...". In the next window we select "Temperature". The process is shown below for our three point monitors:

substratemonitor1 substratemonitor2 diemonitor1 diemonitor2 underfillmonitor1 underfillmonitor2

After adding the three point temperature monitors, they are displayed in the "Monitor" element tree of the Icepak design.

allmonitors

4 Meshing and Running the Thermal Analysis

The next step is generating the mesh. This can be done by clicking the "Generate Mesh" button of the "Simulation" tab as shown below:

generatemesh

After finishing the generation the mesh can be visualized and a window opens, allowing us to observe the Mesh Display and Quality tabs:

aftermesh1

The Quality tab allows to observe the "Face aligment" and "Skewness" metrics of the meshing:

aftermesh2 aftermesh3

The next step is to set up the analysis. For this, we right-click on the "Analysis" Tree Element of the Icepak design and click on "Add Solution Setup..."

addsolsetup

In the dialog that opens we leave the default values for the "General", "Convergence" and "Solver Setting" tabs.

general convergence solversettings

The "Setup1" analysis can be seen now in the "Analysis" tree element of the Icepak design.

We can validate the meshing and the analysis by clicking the "Validate" button in the "Simulation" tab:

validate

There is a warning that the object "Flipchip_BGA1_die_underfill" does not have a mesh. We right-click on the element and click on "Assign Mesh Region". assignmeshregion

We leave the default values on the "SubRegion" window:

asmr2

In the "General" tab of the "Mesh Region" the box "Enable Mesh Function" needs to be ticked:

asmmr3

The resulting mesh is shown below. The new mesh region "MeshRegion1" is displayed in the Mesh tree element.

asmr4

When generating the mesh again, the software is not capable of meshing "MeshRegion1" so we delete and stay with the previous mesh.

To proceed with the simulation we click on "Analyze All":

analyzeall

5 Exploring the results

To observe the results we select the whole package in the viewer, right-click on it and in the route "Plot Fields --> Temperature --> Temperature"

plotfieldtemp1

In the "Create Field Plot" Box we tick the boxes "Specify Name", "Specify Folder" and "Plot on surface only"

plotfieldtemp2

Clicking on the "Surface Smoothing" button, we activate Gaussian smoothing:

gaussiansmoothing

We can now see the temperature plot. As expected the hottest surface is the die and the heat flow towards the outside of the package and the substrate can be seen through the temperature coloring:

![templot1](https://github.com/ABM15/NASSCOM-Packaging/blob/main/Screenshot%202025-04-06%20190347.png templot2 tempplot3

Module 4 - Ensuring Package Reliability: Testing and Performance Validation

There are no exercises prescribed for this module.

Module 5 - Package Design and Modelling: Building a Semiconductor Package from Scratch

The objective of this lab is to build a semiconductor package from scratch. The necessary phases are the following:

  1. Create the die and the substrate in AEDT
  2. Add the die attach material and bond pads
  3. Create the wire bond and assign the material
  4. Apply the mold compound and finalize the package

1 Create the die and the substrate in AEDT

We start the AEDT software and click on the Q3D button to start a Q3D Extractor Design:

aedtstart q3destart

The first step is defining the rectangle of the die with the specified dimensions ( 3mm x 3mm, 0.2 thickness). The easiest way is to graphically draw a rectangle and adjust the position values in the Parameters option of the contextual menu.

ds1 ds2 ds3 ds4

To add the thickness information to the model, the rectangle needs to be selected and we follow the route Modeler-->Surface--> Thicken Sheet...". In the opening window we enter 0.2 mm.

ds5 ds6 ds7 ds8

The material needs to be changed to "silicon" and the name of the rectangle to "Die":

ds9 ds10 ds11 ds12 ds13

The following step is defining the substrate in the specified dimensions (5 mm x 5 mm, 0.5mm thickness). The easiest way is to draw a new rectangle that encompasses the die footprint and adjust the position values in the Parameters option of the contextual menu.

ds14 ds15 ds16

The thickness is added into the model using again the "Modeler-->Surface--> Thicken Sheet.." route after selecting the new rectangle

ds17 ds18

In the resulting geometry the substrate totally encloses the die. Since this does not make sense, since the substrate needs to be at a lower height than the die and not otherwise. A way to correct this is specifying a negative thickness of the same value:

ds19 ds20

The resulting geometry now makes sense. The name of the second rectangle needs to be changed to "Substrate" and the material to "FR4_epoxy":

ds21 ds22

2 Add the die attach material and bond pads

The next step is to create the die attach material. However, in the geometry, the substrate and the die are adjacent so far, which is not totally correct. The substrate position in the vertical axis needs to be lowered by the thickness of the die attach, typically 0.1 mm. We do this in the Properties option of the conextual menu.

da1

Now there is a space between the substrate and the die where to add the die attach material layer:

da2

We create a new rectangle of the same dimensions of the die ( 3mm x 3mm), centered at the origin of coordinates (0,0,0), as the die, but with a negative thickness of 0.1mm:

da3 da4

The material of the new rectangle is changed to "modified_epoxy" and the name to "DieAttach"

da5 da6

The next step is to create the die bond pad. We define a rectangle of dimensions 0.2 mm x 0.2 mm and about 0.5mm into the Y axis. Since it needs to be placed on top of the die, its height is Z=0.2mm.

da7 da9 da10 da11

The next step is to create the substrate bond pad. We define a new rectangle of the same dimensions (0.2 mm x 0.2 mm) but placed on the substrate, that is, Z=-0.1mm.

da12

Both bond pad rectangles are renamed:

da13 da14

3 Create the wire bond and assign the material

The next step is to create the wire bond between the previously created die and substrate bond pads. For that we click on the "Draw Bondwire" button at the "Draw" tab.

wb1

We trace a line connecting both bond pads:

wb2

A Bondwire dialog window appears. We accept the defaults for the JEDEC4 norm.

wb3

The bond wire is created:

wb4 wb5

To illustrate better the real layout we define a second die bond pad of the same dimensions (0.2mm x 0.2mm), 0.5mm into the X axis:

wb6 wb7

Finally we change the material of the bond wire from "copper" to "gold":

wb8 wb9 wb10

4 Apply mold compound and finalize the package model

The last step is to create the mold compound as the outermost component of the package, sitting on top of the substrate. We define a new rectangle of the same dimensions of the substrate (5mm x 5mm) and starting at Z=-0.1mm , with a thickness of 1.2 mm, which is enough to enclose the die attach, the die, and the wire bond, protecting the package.

mc1 mc2 mc3

We observe the resulting geometry:

mc4

The name of the new rectangle needs to be changed to "MoldCompound" and the material to "epoxy_Kevlar_xy"

mc5

Selecting an internal component, for example, the die bond pad, we can inspect the final geometry in 3D:

mc6 mc7 mc8

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Repository for the VSD NASSCOM Semiconductor Packaging Workshop (03/28/2025-04/06/2025)

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