Skip to content

Commit cf1cbcd

Browse files
fpistmfpistm
authored
Merge pull request #2213 from fpistm/STM32CubeF4_update
chore(F4): update to latest STM32CubeF4 v1.28.0
2 parents 20339e8 + f79dbe1 commit cf1cbcd

File tree

181 files changed

+12024
-17900
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

181 files changed

+12024
-17900
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - peripherals registers declarations and bits definition
10-
* - Macros to access peripheral’s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
@@ -34,7 +34,7 @@
3434
#define __STM32F401xC_H
3535

3636
#ifdef __cplusplus
37-
extern "C" {
37+
extern "C" {
3838
#endif /* __cplusplus */
3939

4040
/** @addtogroup Configuration_section_for_CMSIS
@@ -64,7 +64,7 @@
6464
*/
6565
typedef enum
6666
{
67-
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
67+
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
6868
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
6969
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
7070
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
@@ -73,7 +73,7 @@ typedef enum
7373
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
7474
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
7575
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
76-
/****** STM32 specific Interrupt Numbers **********************************************************************/
76+
/****** STM32 specific Interrupt Numbers **********************************************************************/
7777
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
7878
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
7979
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
@@ -129,7 +129,7 @@ typedef enum
129129
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
130130
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
131131
FPU_IRQn = 81, /*!< FPU global interrupt */
132-
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
132+
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
133133
} IRQn_Type;
134134

135135
/**
@@ -203,7 +203,7 @@ typedef struct
203203
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
204204
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
205205
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
206-
}DBGMCU_TypeDef;
206+
} DBGMCU_TypeDef;
207207

208208

209209
/**
@@ -822,9 +822,9 @@ typedef struct
822822
* @}
823823
*/
824824

825-
/** @addtogroup Peripheral_Registers_Bits_Definition
826-
* @{
827-
*/
825+
/** @addtogroup Peripheral_Registers_Bits_Definition
826+
* @{
827+
*/
828828

829829
/******************************************************************************/
830830
/* Peripheral Registers_Bits_Definition */
@@ -1400,7 +1400,7 @@ typedef struct
14001400

14011401
/******************* Bit definition for CRC_IDR register ********************/
14021402
#define CRC_IDR_IDR_Pos (0U)
1403-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
1403+
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
14041404
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
14051405

14061406

@@ -3915,7 +3915,7 @@ typedef struct
39153915
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
39163916
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
39173917
/*
3918-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
3918+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
39193919
*/
39203920
#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
39213921

@@ -4291,7 +4291,7 @@ typedef struct
42914291
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
42924292
/******************** Bit definition for RCC_AHB2ENR register ***************/
42934293
/*
4294-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
4294+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
42954295
*/
42964296
#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
42974297

‎system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - peripherals registers declarations and bits definition
10-
* - Macros to access peripheral’s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
@@ -34,7 +34,7 @@
3434
#define __STM32F401xE_H
3535

3636
#ifdef __cplusplus
37-
extern "C" {
37+
extern "C" {
3838
#endif /* __cplusplus */
3939

4040
/** @addtogroup Configuration_section_for_CMSIS
@@ -64,7 +64,7 @@
6464
*/
6565
typedef enum
6666
{
67-
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
67+
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
6868
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
6969
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
7070
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
@@ -73,7 +73,7 @@ typedef enum
7373
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
7474
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
7575
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
76-
/****** STM32 specific Interrupt Numbers **********************************************************************/
76+
/****** STM32 specific Interrupt Numbers **********************************************************************/
7777
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
7878
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
7979
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
@@ -129,7 +129,7 @@ typedef enum
129129
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
130130
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
131131
FPU_IRQn = 81, /*!< FPU global interrupt */
132-
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
132+
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
133133
} IRQn_Type;
134134

135135
/**
@@ -203,7 +203,7 @@ typedef struct
203203
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
204204
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
205205
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
206-
}DBGMCU_TypeDef;
206+
} DBGMCU_TypeDef;
207207

208208

209209
/**
@@ -822,9 +822,9 @@ typedef struct
822822
* @}
823823
*/
824824

825-
/** @addtogroup Peripheral_Registers_Bits_Definition
826-
* @{
827-
*/
825+
/** @addtogroup Peripheral_Registers_Bits_Definition
826+
* @{
827+
*/
828828

829829
/******************************************************************************/
830830
/* Peripheral Registers_Bits_Definition */
@@ -1400,7 +1400,7 @@ typedef struct
14001400

14011401
/******************* Bit definition for CRC_IDR register ********************/
14021402
#define CRC_IDR_IDR_Pos (0U)
1403-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
1403+
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
14041404
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
14051405

14061406

@@ -3915,7 +3915,7 @@ typedef struct
39153915
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
39163916
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
39173917
/*
3918-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
3918+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
39193919
*/
39203920
#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
39213921

@@ -4291,7 +4291,7 @@ typedef struct
42914291
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
42924292
/******************** Bit definition for RCC_AHB2ENR register ***************/
42934293
/*
4294-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
4294+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
42954295
*/
42964296
#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
42974297

‎system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
* This file contains:
88
* - Data structures and the address mapping for all peripherals
99
* - peripherals registers declarations and bits definition
10-
* - Macros to access peripheral’s registers hardware
10+
* - Macros to access peripheral's registers hardware
1111
*
1212
******************************************************************************
1313
* @attention
@@ -34,7 +34,7 @@
3434
#define __STM32F405xx_H
3535

3636
#ifdef __cplusplus
37-
extern "C" {
37+
extern "C" {
3838
#endif /* __cplusplus */
3939

4040
/** @addtogroup Configuration_section_for_CMSIS
@@ -64,7 +64,7 @@
6464
*/
6565
typedef enum
6666
{
67-
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
67+
/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
6868
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
6969
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
7070
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
@@ -73,7 +73,7 @@ typedef enum
7373
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
7474
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
7575
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
76-
/****** STM32 specific Interrupt Numbers **********************************************************************/
76+
/****** STM32 specific Interrupt Numbers **********************************************************************/
7777
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
7878
PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
7979
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
@@ -314,7 +314,7 @@ typedef struct
314314
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
315315
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
316316
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
317-
}DBGMCU_TypeDef;
317+
} DBGMCU_TypeDef;
318318

319319

320320
/**
@@ -1052,9 +1052,9 @@ typedef struct
10521052
* @}
10531053
*/
10541054

1055-
/** @addtogroup Peripheral_Registers_Bits_Definition
1056-
* @{
1057-
*/
1055+
/** @addtogroup Peripheral_Registers_Bits_Definition
1056+
* @{
1057+
*/
10581058

10591059
/******************************************************************************/
10601060
/* Peripheral Registers_Bits_Definition */
@@ -1066,7 +1066,7 @@ typedef struct
10661066
/* */
10671067
/******************************************************************************/
10681068
/*
1069-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1069+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
10701070
*/
10711071
#define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
10721072

@@ -5327,7 +5327,7 @@ typedef struct
53275327

53285328
/******************* Bit definition for CRC_IDR register ********************/
53295329
#define CRC_IDR_IDR_Pos (0U)
5330-
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5330+
#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
53315331
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
53325332

53335333

@@ -5342,7 +5342,7 @@ typedef struct
53425342
/* */
53435343
/******************************************************************************/
53445344
/*
5345-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5345+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
53465346
*/
53475347
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
53485348
/******************** Bit definition for DAC_CR register ********************/
@@ -9181,7 +9181,7 @@ typedef struct
91819181
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
91829182
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
91839183
/*
9184-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9184+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
91859185
*/
91869186
#define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
91879187

@@ -9629,7 +9629,7 @@ typedef struct
96299629
#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
96309630
/******************** Bit definition for RCC_AHB2ENR register ***************/
96319631
/*
9632-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9632+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
96339633
*/
96349634
#define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
96359635

@@ -9642,7 +9642,7 @@ typedef struct
96429642

96439643
/******************** Bit definition for RCC_AHB3ENR register ***************/
96449644
/*
9645-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
9645+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
96469646
*/
96479647
#define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
96489648

@@ -10075,7 +10075,7 @@ typedef struct
1007510075
/* */
1007610076
/******************************************************************************/
1007710077
/*
10078-
* @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
10078+
* @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
1007910079
*/
1008010080
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
1008110081
#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
@@ -14272,7 +14272,7 @@ typedef struct
1427214272
#define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
1427314273
#define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
1427414274
#define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
14275-
#define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
14275+
#define FLASH_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
1427614276

1427714277
#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
1427814278
#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */

0 commit comments

Comments
 (0)