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Update CMSIS Cortex-Mx Device Peripheral Access Layer System Source File
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 01566b3 commit 26041d3

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7 files changed

+92
-185
lines changed

7 files changed

+92
-185
lines changed

‎system/STM32F0xx/system_stm32f0xx.c‎

Lines changed: 9 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
*
77
* 1. This file provides two functions and one global variable to be called from
88
* user application:
9-
* - SystemInit(): This function is called at startup just after reset and
9+
* - SystemInit(): This function is called at startup just after reset and
1010
* before branch to main program. This call is made inside
1111
* the "startup_stm32f0xx.s" file.
1212
*
@@ -101,7 +101,7 @@
101101
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
102102
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
103103
Note: If you use this function to configure the system clock there is no need to
104-
call the 2 first functions listed above, since SystemCoreClock variable is
104+
call the 2 first functions listed above, since SystemCoreClock variable is
105105
updated automatically.
106106
*/
107107
uint32_t SystemCoreClock = 8000000;
@@ -132,63 +132,12 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
132132
*/
133133
void SystemInit(void)
134134
{
135-
/* Reset the RCC clock configuration to the default reset state ------------*/
136-
/* Set HSION bit */
137-
RCC->CR |= (uint32_t)0x00000001U;
138-
139-
#if defined (STM32F051x8) || defined (STM32F058x8)
140-
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
141-
RCC->CFGR &= (uint32_t)0xF8FFB80CU;
142-
#else
143-
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
144-
RCC->CFGR &= (uint32_t)0x08FFB80CU;
145-
#endif /* STM32F051x8 or STM32F058x8 */
146-
147-
/* Reset HSEON, CSSON and PLLON bits */
148-
RCC->CR &= (uint32_t)0xFEF6FFFFU;
149-
150-
/* Reset HSEBYP bit */
151-
RCC->CR &= (uint32_t)0xFFFBFFFFU;
152-
153-
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
154-
RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
155-
156-
/* Reset PREDIV[3:0] bits */
157-
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
158-
159-
#if defined (STM32F072xB) || defined (STM32F078xx)
160-
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
161-
RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
162-
#elif defined (STM32F071xB)
163-
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
164-
RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
165-
#elif defined (STM32F091xC) || defined (STM32F098xx)
166-
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
167-
RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
168-
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
169-
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
170-
RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
171-
#elif defined (STM32F051x8) || defined (STM32F058xx)
172-
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
173-
RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
174-
#elif defined (STM32F042x6) || defined (STM32F048xx)
175-
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
176-
RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
177-
#elif defined (STM32F070x6) || defined (STM32F070xB)
178-
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
179-
RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
180-
/* Set default USB clock to PLLCLK, since there is no HSI48 */
181-
RCC->CFGR3 |= (uint32_t)0x00000080U;
182-
#else
183-
#warning "No target selected"
184-
#endif
185-
186-
/* Reset HSI14 bit */
187-
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
188-
189-
/* Disable all interrupts */
190-
RCC->CIR = 0x00000000U;
191-
135+
/* NOTE :SystemInit(): This function is called at startup just after reset and
136+
before branch to main program. This call is made inside
137+
the "startup_stm32f0xx.s" file.
138+
User can setups the default system clock (System clock source, PLL Multiplier
139+
and Divider factors, AHB/APBx prescalers and Flash settings).
140+
*/
192141
}
193142

194143
/**
@@ -271,7 +220,7 @@ void SystemCoreClockUpdate (void)
271220
#else
272221
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
273222
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
274-
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
223+
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
275224
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
276225
STM32F091xC || STM32F098xx || STM32F030xC */
277226
}

‎system/STM32F3xx/system_stm32f3xx.c‎

Lines changed: 0 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,6 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
138138

139139
/**
140140
* @brief Setup the microcontroller system
141-
* Initialize the FPU setting, vector table location and the PLL configuration is reset.
142141
* @param None
143142
* @retval None
144143
*/
@@ -149,31 +148,6 @@ void SystemInit(void)
149148
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
150149
#endif
151150

152-
/* Reset the RCC clock configuration to the default reset state ------------*/
153-
/* Set HSION bit */
154-
RCC->CR |= 0x00000001U;
155-
156-
/* Reset CFGR register */
157-
RCC->CFGR &= 0xF87FC00CU;
158-
159-
/* Reset HSEON, CSSON and PLLON bits */
160-
RCC->CR &= 0xFEF6FFFFU;
161-
162-
/* Reset HSEBYP bit */
163-
RCC->CR &= 0xFFFBFFFFU;
164-
165-
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
166-
RCC->CFGR &= 0xFF80FFFFU;
167-
168-
/* Reset PREDIV1[3:0] bits */
169-
RCC->CFGR2 &= 0xFFFFFFF0U;
170-
171-
/* Reset USARTSW[1:0], I2CSW and TIMs bits */
172-
RCC->CFGR3 &= 0xFF00FCCCU;
173-
174-
/* Disable all interrupts */
175-
RCC->CIR = 0x00000000U;
176-
177151
#ifdef VECT_TAB_SRAM
178152
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
179153
#else

‎system/STM32F4xx/system_stm32f4xx.c‎

Lines changed: 6 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -22,29 +22,13 @@
2222
******************************************************************************
2323
* @attention
2424
*
25-
* <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
25+
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
26+
* All rights reserved.</center></h2>
2627
*
27-
* Redistribution and use in source and binary forms, with or without modification,
28-
* are permitted provided that the following conditions are met:
29-
* 1. Redistributions of source code must retain the above copyright notice,
30-
* this list of conditions and the following disclaimer.
31-
* 2. Redistributions in binary form must reproduce the above copyright notice,
32-
* this list of conditions and the following disclaimer in the documentation
33-
* and/or other materials provided with the distribution.
34-
* 3. Neither the name of STMicroelectronics nor the names of its contributors
35-
* may be used to endorse or promote products derived from this software
36-
* without specific prior written permission.
37-
*
38-
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
39-
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40-
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
41-
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
42-
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
43-
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
44-
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
45-
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
46-
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47-
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28+
* This software component is licensed by ST under BSD 3-Clause license,
29+
* the "License"; You may not use this file except in compliance with the
30+
* License. You may obtain a copy of the License at:
31+
* opensource.org/licenses/BSD-3-Clause
4832
*
4933
******************************************************************************
5034
*/
@@ -163,24 +147,6 @@ void SystemInit(void)
163147
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
164148
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
165149
#endif
166-
/* Reset the RCC clock configuration to the default reset state ------------*/
167-
/* Set HSION bit */
168-
RCC->CR |= (uint32_t)0x00000001;
169-
170-
/* Reset CFGR register */
171-
RCC->CFGR = 0x00000000;
172-
173-
/* Reset HSEON, CSSON and PLLON bits */
174-
RCC->CR &= (uint32_t)0xFEF6FFFF;
175-
176-
/* Reset PLLCFGR register */
177-
RCC->PLLCFGR = 0x24003010;
178-
179-
/* Reset HSEBYP bit */
180-
RCC->CR &= (uint32_t)0xFFFBFFFF;
181-
182-
/* Disable all interrupts */
183-
RCC->CIR = 0x00000000;
184150

185151
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
186152
SystemInit_ExtMemCtl();

‎system/STM32F7xx/system_stm32f7xx.c‎

Lines changed: 6 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -22,29 +22,13 @@
2222
******************************************************************************
2323
* @attention
2424
*
25-
* <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
25+
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
26+
* All rights reserved.</center></h2>
2627
*
27-
* Redistribution and use in source and binary forms, with or without modification,
28-
* are permitted provided that the following conditions are met:
29-
* 1. Redistributions of source code must retain the above copyright notice,
30-
* this list of conditions and the following disclaimer.
31-
* 2. Redistributions in binary form must reproduce the above copyright notice,
32-
* this list of conditions and the following disclaimer in the documentation
33-
* and/or other materials provided with the distribution.
34-
* 3. Neither the name of STMicroelectronics nor the names of its contributors
35-
* may be used to endorse or promote products derived from this software
36-
* without specific prior written permission.
37-
*
38-
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
39-
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40-
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
41-
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
42-
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
43-
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
44-
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
45-
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
46-
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47-
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28+
* This software component is licensed by ST under BSD 3-Clause license,
29+
* the "License"; You may not use this file except in compliance with the
30+
* License. You may obtain a copy of the License at:
31+
* opensource.org/licenses/BSD-3-Clause
4832
*
4933
******************************************************************************
5034
*/
@@ -147,24 +131,6 @@ void SystemInit(void)
147131
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
148132
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
149133
#endif
150-
/* Reset the RCC clock configuration to the default reset state ------------*/
151-
/* Set HSION bit */
152-
RCC->CR |= (uint32_t)0x00000001;
153-
154-
/* Reset CFGR register */
155-
RCC->CFGR = 0x00000000;
156-
157-
/* Reset HSEON, CSSON and PLLON bits */
158-
RCC->CR &= (uint32_t)0xFEF6FFFF;
159-
160-
/* Reset PLLCFGR register */
161-
RCC->PLLCFGR = 0x24003010;
162-
163-
/* Reset HSEBYP bit */
164-
RCC->CR &= (uint32_t)0xFFFBFFFF;
165-
166-
/* Disable all interrupts */
167-
RCC->CIR = 0x00000000;
168134

169135
/* Configure the Vector Table location add offset address ------------------*/
170136
#ifdef VECT_TAB_SRAM

‎system/STM32G0xx/system_stm32g0xx.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -243,8 +243,10 @@ void SystemCoreClockUpdate(void)
243243
}
244244
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
245245
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
246+
246247
SystemCoreClock = pllvco/pllr;
247248
break;
249+
248250
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
249251
default: /* HSI used as system clock */
250252
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));

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