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Commits on Oct 20, 2021

• axi_i2s_adi: initialize cdc_sync_stage0_tick bits to '0'

  corna

  committed
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• axi_hdmi_tx: Add UltraScale+ architecture to Verilog

  corna

  committed
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Commits on Oct 18, 2021

• ad4630_fmc: Initial commit

  

  Istvan Csomortani

  authored and

  sarpadi

  committed
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• ad463x_data_capture: Initial commit

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  Istvan Csomortani

  authored and

  sarpadi

  committed
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• spi_engine_execution: Delete control loop-back in sdi_data_valid generation

  

  Istvan Csomortani

  authored and

  sarpadi

  committed
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• axi_spi_engine: Add generic config params

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  sarpadi

  committed
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• spi_engine/data_reorder: Initial commit

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  Istvan Csomortani

  authored and

  sarpadi

  committed
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• library/tb: Improve run_tb.sh

  

  Istvan Csomortani

  authored and

  sarpadi

  committed
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Commits on Oct 15, 2021

• daq2/zcu102: Fix the ad9144 data offload to use internal BRAM

  mihnagy

  committed
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• daq2/kcu105: Fix the ad9144 data offload to use internal BRAM

  mihnagy

  committed
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• daq2/kc705: Fix the ad9144 data offload to use internal bram

  mihnagy

  committed
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• daq2/zc706: Increase BRAM utilization to 52%

  mihnagy

  committed
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Commits on Oct 12, 2021

• scripts: Add logic for vivado version check

  

  LIacob106

  authored and

  FilipG24

  committed
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Commits on Oct 8, 2021

• Revert "data_offload: Fix timing violation"

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  ronagyl

  committed
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Commits on Oct 7, 2021

• scripts/adi_board.tcl: For older families stick with axi_interconnect

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  ronagyl

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• jesd204_rx: fixed makefile

  FilipG24

  committed
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Commits on Oct 6, 2021

• jesd204/ad_ip_jesd204_tpl : Add support for 12 lanes

  ronagyl

  committed
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Commits on Oct 5, 2021

• projects/ad9081_fmca_ebz: Updated makefiles

  FilipG24

  committed
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• Makefile: Fix misc makefiles from projects and library

  ronagyl

  committed
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• jesd204/jesd204_rx: Define tie off values for unused ports

  ronagyl

  committed
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• jesd204/jesd204_tx/jesd204_tx.v: Have FFs initial value, useful for simulation

  ronagyl

  committed
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• ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock

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  ronagyl

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• ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock

  ronagyl

  committed
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• ad9081_fmca_ebz/vck190: Initial version

  ronagyl

  committed
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• ad9081_fmca_ebz/common: Add Versal transceiver support

  ronagyl

  committed
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• jesd204:jesd204_versal_gt_adapter_rx/tx: Add adapter for Versal transceiver IP

  ronagyl

  committed
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• common/vck190: Initial version

  ronagyl

  committed
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• common/vmk180_es1: Initial version

  ronagyl

  committed
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• common/vmk180: Initial version

  ronagyl

  committed
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• scripts/adi_project_xilinx.tcl: VCK190 support

  ronagyl

  committed
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• scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode

  ronagyl

  committed
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• scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support

  ronagyl

  committed
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• scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect

  ronagyl

  committed
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• scripts/adi_xilinx_device_info_enc.tcl: Add Versal support

  ronagyl

  committed
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• scripts/adi_ip_xilinx.tcl: Enable auto family support

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  ronagyl

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