pytv/
lib.rs

1//! Python Templated Verilog
2//! 
3//! # Generation Process
4//! ```txt
5//! .pytv ----> .v.py --+-> .v
6//!                     |
7//!                     +-> .inst
8//! ```
9//! 
10//! # Examples
11//! ```txt
12//! //! a = 1 + 2;            #  Python inline
13//! assign wire_`a` = wire_b; // Verilog with variable/expression substitute
14//! /*!
15//! b = a ** 2;               #  Python block
16//! */
17//! ```
18//! The magic comment string can be configured (`!` as default).
19//! 
20//! # Related Auto Generator Projects
21//! - **FLAMES**: template-based C++ library for Vitis HLS
22//!   [[website](https://flames.autohdw.com)]
23//!   [[GitHub](https://github.com/autohdw/flames)]
24//!   [[paper at IEEE](https://ieeexplore.ieee.org/document/10437992)]
25//!   [[paper PDF](https://wqzhao.org/assets/zhao2024flexible.pdf)]
26//! - **AHDW**: a DSL, the predecessor of this project
27//!   [[paper at IEEE](https://ieeexplore.ieee.org/document/10396119)]
28//!   [[paper PDF](https://wqzhao.org/assets/zhao2023automatic.pdf)]
29
30mod config;
31mod convert;
32
33#[cfg(feature = "inst")]
34mod inst;
35
36pub use config::Config;
37pub use config::FileOptions;
38pub use convert::Convert;