My Submission for the Minimal Fab Design Contest 2024
Updated 2025-02-12 11:53:43 +01:00
A small example of how to use KLayout for the layout of a simple inverter and run DRC and LVS for Sky130.
Updated 2024-12-03 05:49:00 +01:00
Schematic and layout for a NAND gate using the ICPS PDK
Updated 2024-12-03 05:44:34 +01:00
Updated 2024-12-03 05:33:23 +01:00
Open hardware FPGA development board with Lattice iCE40UP5k.
Based on the awesome iCEBreaker and iCEBreaker-bitsy!
Updated 2024-12-03 05:33:10 +01:00
Updated 2024-12-03 05:28:22 +01:00
This repository contains FPGA examples for LeoRV32.
Updated 2024-12-03 05:24:01 +01:00
Verification environment for the LeoRV32 RISC-V CPU
Updated 2024-12-03 05:23:59 +01:00
A simple RV32I RISC-V CPU written in SystemVerilog
Updated 2024-12-03 05:23:58 +01:00
A project for the submission to the Efabless Open MPW Program
Updated 2024-12-03 05:23:44 +01:00